The detection of circuit board manufacturing defects is a long-established and standardized industry practice. The industry standard practices for these methods are described in IEEE Standard 1149. This standard method of testing is often referred to as JTAG in reference to the Joint Test Action Group standards committee from which it originated. That standard stipulates the test methodology and interface protocols for implementing different types of test functions that allow a board manufacturer to verify that circuit boards and associated integrated circuits (“ICs”) are manufactured properly. The JTAG standard is specific to CMOS logic circuits—unfortunately, the JTAG standard does not address in detail the testing of analog or AC coupled circuitry.
One aspect of the standard involves the verification of the board level interconnect between ICs. In the methodology described in the standard it is assumed that the connection between the ICs is a DC coupled connection and that the signal levels are commensurate with standard CMOS logic. In these instances the standard calls for a boundary scan cell to be placed at the input and output (“I/O”) pins of the interconnect. The dedicated test interface then allows the tester to force a specified DC logic level out of the driving IC and to determine the logic level received at the input end of the connection. If the correct anticipated pattern is received, then the interconnect is deemed to be manufactured correctly and to be viable.
There are, however, a significant number of instances where interconnect signals between ICs are AC coupled and do not conform to CMOS logic levels. AC coupled circuits typically require a coupling capacitor between circuits to block DC current during the transmission of AC signals. An example would be an AC coupled high-speed differential current mode logic (“CML”) level interface between a physical media dependent (“PMD”) device and a physical layer (“PHY”) device in a data communication link. In this situation the prescribed DC CMOS logic test methodologies would not be successful in verifying the connection. Consequently, a different approach is required for testing the AC interconnection between CMOS logic circuits or CMOS ICs.
One recent proposal has been made for adaptation or modification of the JTAG standard to permit the introduction of an alternating AC signal into non-CMOS logic level AC coupled interconnects. This proposal may be termed “ACJTAG”. The signal is synchronously sampled on the receiver side at intervals to determine if the signal was appropriate to the anticipated interconnect. If the received pattern is consistent with expectations, the interconnect is deemed correct. Otherwise, the assumption is made that there is a defect in the interconnect between the ICs under test. However, this proposal has not set forth a means and mode for interconnection of the test logic to high speed AC coupled signal lines.
Our invention enables the detection and interfacing of high-speed AC coupled non-CMOS logic level signals into ACJTAG logic by allowing an alternating AC signal to be driven onto non-CMOS logic level AC coupled interconnects; it is applicable as well to non-CMOS level single-ended and differential signals with or without AC coupling. This AC signal is synchronously sampled on the receiver side at intervals to determine if the signal is appropriate to the anticipated interconnect. If the received pattern is consistent with expectations, the interconnect is deemed correct. Otherwise it is assumed that there is an issue with the manufacturing process.
While the above proposal outlines the digital portion of the test methodology, it does not define how to interface the logic to the high-speed AC coupled signal lines.